The pattern effect to the integrated circuit manufacturing processes has been well known as micro-loading effect, which occurs due to differences in pattern densities in a wafer. The micro-loading effect pertains to a phenomenon occurring upon simultaneously exposing, etching and/or polishing a pattern of a higher density and a pattern of a lower density. Due to a difference in exposure/etching/polishing rate of a film from one location to another, the amount of reaction produced by the exposure/etching/polishing becomes locally dense or sparse, and hence causes a non-uniformity in etching/polish rates or pattern dimension after exposure. Big variations in effective pattern densities may result in significant and undesirable effects such as pattern dimension deviation and thickness variation.
To counteract this effect, a layout design step known as dummy insertion was developed, during which the circuit layout is modified and dummy patterns are inserted to locations with low pattern density. The insertion of dummy patterns helps achieve uniform effective pattern density across the wafer, therefore avoiding problems.
Typically, after a design house finishes a design of an integrated circuit, a graphic data system (GDS) file, which is a binary file including the layout of the integrated circuit, is generated. A program may be used to insert dummy patterns. After the dummy patterns are inserted, design houses may provide (tape-out) the GDS files to a foundry. Masks are then generated by the foundry or mask vendors.
Dummy patterns may be divided into OD dummy patterns, poly dummy patterns, metal dummy patterns, etc. OD dummy patterns are dummy active region patterns, poly dummy patterns include patterns of polysilicon gates for forming gates of transistors, and metal dummy patterns are patterns of metal features in metallization layers. OD dummy patterns and poly dummy patterns are often operated together. Using OD dummy patterns as an example, typically, to insert dummy patterns, the dummy insertion program needs to find out the main patterns of ODs and polys, and then looks for areas that do not contain ODs and polys to insert OD dummy patterns. FIG. 1 illustrates three types of dummy cells used for ODs and polys. Dummy cell 1 includes dummy poly region 10 and dummy OD ring 12 encircling dummy poly region 10. Dummy cell 2 includes dummy poly region 14 and dummy OD ring 16 encircling dummy poly region 14. Dummy cell 2 is significantly smaller than cell 1. Polysilicon formation is more sensitive to the pattern density, and thus needs more uniformly distributed dummy poly patterns. Accordingly, cell 3 is a dummy poly pattern, which is not dispatched together with a dummy OD pattern.
In a conventional (forward) dummy insertion process, the dummy insertion program looks into the GDS file, and inserts dummy pattern cells 1 wherever they can be inserted without violating design rules. The dummy insertion program then looks for regions that are not big enough for dummy pattern cell 1, but are big enough for dummy pattern cell 2, and insert dummy pattern cells 2. For the insertion of dummy polysilicon, the dummy insertion program may need to find regions that are not big enough for dummy pattern cells 1 and 2, but are big enough to insert dummy poly pattern cell 3.
FIG. 2 illustrates an OD mask pattern including inserted dummy OD patterns, wherein only the patterns of active regions and dummy active regions, are shown. Region 20 is a device region, and is referred to as a main pattern. Squares 22 are dummy patterns of cell 1, and squares 24 are dummy pattern cells 2. If a poly mask instead of an OD mask is shown, dummy pattern cells 3 may also be found.
The conventional dummy insertion scheme suffers from drawbacks. First, inserting dummy patterns is typically a long process that may take several hours or even days. Therefore, foundries often provide the program dummy insertions to the design houses, and allow design houses to insert dummy patterns by themselves. The proprietary information of how dummy patterns are inserted is thus exposed. Second, after inserting dummy patterns, the sizes of GDS files are increased drastically, often from about one Gbits or less to tens of Gbits. This not only consumes huge storage, it is also much harder to find a computer to process such big files. Thirdly, as is shown in FIG. 2, the dummy patterns are not uniformly inserted. This causes adverse effects to the critical dimension uniformity control and chemical mechanical polish uniformity control. New dummy insertion methods for solving the above-discussed problems are thus needed.